1. Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to performing efficient timing calculations in numerical sequential cell sizing and performing efficient incremental slack margin propagation.
2. Related Art
The goal of circuit synthesis is to convert a high-level description of a circuit design into an implementation that meets a set of timing constraints, and at the same time optionally optimizes one or more metrics, such as area, leakage power, etc.
Some circuit synthesis approaches create an initial circuit design at a given abstraction level (e.g., a logical or physical design). Next, a cell is identified in the circuit design for optimization based on the metrics that are desired to be optimized. An optimal size for the identified cell is then determined by iteratively replacing the identified cell with functionally equivalent cells that have different sizes (this optimization process is also referred to as “sizing the cell,” “sizing the gate,” etc.). For each replacement cell size that is tried, the circuit synthesis approach updates timing information (often throughout the entire circuit design), and rejects cell sizes for which one or more timing constraints are violated. The iterative optimization process typically terminates after the optimization process has executed for a certain number of iterations or for a certain amount of time.
Iterative trial-and-error based circuit optimization processes often take too long to complete and/or produce poor quality results for large circuit designs in which timing constraints are checked across many process corners and modes. Therefore, there is a need to improve the efficiency of calculations that are performed during circuit optimization.